In general, integrated circuits that perform arithmetic or other operations in synchronism with an operation clock are designed with large margins so that they always operate normally even in the presence of variations originating from the fabrication process, variations in the supply voltage, variations in temperature, and other factors. That is, such an integrated circuit is so designed that, even if a variation or other factor as mentioned above causes an increase in a delay time within its circuit, the operation of the integrated circuit as a whole is complete within one clock of its operation clock. Moreover, such an integrated circuit is supplied with a sufficiently high supply voltage so that it operates normally even when all conditions as mentioned above are at their worst.
Designing an integrated circuit with large margins and supplying it with a high supply voltage as described above, however, hinder achieving a higher operation rate and lower power consumption in it. To overcome this inconvenience, voltage conversion circuits have been under development that monitor the operation status of an integrated circuit and control the supply voltage thereto in such a way that the integrated circuit is supplied with the minimum drive voltage that it requires for normal operation.
FIG. 24 is a diagram showing an outline of the configuration of an example of a conventional voltage conversion circuit. The voltage conversion circuit shown in this figure is a prior-art technique disclosed in Japanese Patent Application Laid-Open No. H10-242831, and includes a duty ratio control circuit 901, a buffer circuit 902, a filter circuit 903, a critical path circuit 904, a delay circuit 905, a true/false judgment circuit 906, and an adder 907.
The duty ratio control circuit 901 is a circuit that controls the buffer circuit 902 to vary its output voltage, and includes a counter and a comparator circuit. The counter counts from 0 to 2n−1 (for example, when n=6, from 0 to 63) by incrementing its count every period of a clock signal (not shown) fed thereto, and then feeds the count, in the form of an n-bit signal NA, to the comparator circuit. Here, after 2n−1, the count returns to 0. The comparator circuit receives, in addition to the signal NA, an n-bit signal NB from the adder 907.
The comparator circuit is a circuit that controls the on/off states of a PMOS transistor M1 and an NMOS transistor M2 that together constitute the buffer circuit 902. The comparator circuit feeds control signals X1 and X2 to the gates of the transistors M1 and M2, respectively. The comparator circuit turns the levels of the control signals X1 and X2 to low when the signal NA is 0, and turns the levels of the control signals X1 and X2 to high when the signal NA coincides with the signal NB.
In the buffer circuit 902, the PMOS transistor M1 receives a first supply voltage at its source, and the NMOS transistor M2 receives a second supply voltage (here, the ground voltage) at its source. The drains of these two transistors are connected together, and the node at which they are connected together serves as the output end of the buffer circuit 902.
Accordingly, when the control signals X1 and X2 are low, the PMOS transistor M1 is on, and the NMOS transistor M2 is off. Thus, the output voltage of the buffer circuit 902 is roughly equal to the first supply voltage. On the other hand, when the control signals X1 and X2 are high, the PMOS transistor M1 is off, and the NMOS transistor M2 is on. Thus, the output voltage of the buffer circuit 902 is roughly equal to the second supply voltage (the ground voltage). As a result, the output voltage of the buffer circuit 902 is a pulsating voltage signal Y that rises when the signal NA becomes 0 and that falls when the signal NA becomes equal to the signal NB.
This voltage signal Y is smoothed by the filter circuit 903, which is composed of an inductor L1 and a capacitor C1, and is thereby formed into an output voltage Z. The output voltage Z is fed to an internal circuit (not shown) formed on the same circuit board so as to be used as the drive voltage of the internal circuit. The output voltage Z is also used as the supply voltage to the critical path circuit 904.
Let the length of time for which the PMOS transistor M1 remains on and the NMOS transistor M2 remains off (i.e., the length of time for which the control signals X1 and X2 remain low) be T1, called the turn-on time, and the length of time for which the PMOS transistor M1 remains off and the NMOS transistor M2 remains on (i.e., the length of time for which the control signals X1 and X2 remain high) be T2, called the turn-off time. Then, the output voltage Z of the filter circuit 903 is generally given by formula (1) below.
                    Z        =                              T1                          T1              +              T2                                ×          VDD                                    (        1        )            
In this formula, the turn-on time T1 (the numerator of the right side) represents the pulse width of the voltage signal Y, and the sum T1+T2 (the denominator of the right side) of the turn-on time T1 and the turn-off time T2 represents the pulse period of the voltage signal Y. That is, this formula indicates that the output voltage Z can be controlled by controlling the ratio (hereinafter called the duty ratio) of the pulse width to the pulse period of the voltage signal Y.
In the voltage conversion circuit configured as described above, by varying the value of the signal NB fed from the adder 907 to the comparator circuit of the duty ratio control circuit 901, the turn-on time T1 (the pulse width) is varied, and thereby the duty ratio of the voltage signal Y output from the buffer circuit 902 is controlled. In this way, it is possible to control the drive voltage (the output voltage Z) fed to the internal circuit (hereinafter, this method of controlling a duty ratio will be called the pulse width varying method). Here, as the means for setting the signal NB at the optimum value is adopted a method relying on detection of the operation rate of the critical path circuit 904.
The critical path circuit 904 is a circuit that serves as a duplicate of the path circuit that is considered to cause the longest delay to the signal passing therethrough within the internal circuit to which the output voltage Z is fed. As described above, the critical path circuit 904 receives, as its supply voltage, the output voltage Z of the filter circuit 903. That is, the critical path circuit 904 monitors the drive voltage of the internal circuit, which is the target to which the supply voltage is supplied. Here, it is assumed that the operable voltage of the critical path circuit 904 is equal to that of the internal circuit.
When the critical path circuit 904 can operate from the output voltage Z of the filter circuit 903, the critical path circuit 904 feeds predetermined data to the true/false judgment circuit 906. Here, the true/false judgment circuit 906 receives the data fed from the critical path circuit 904 not only directly but also through the delay circuit 905 and thus with a predetermined delay, i.e., as delayed data.
If the true/false judgment circuit 906 does not receive the data directly from the critical path circuit 904, the true/false judgment circuit 906 judges that the internal circuit, to which the supply voltage is being supplied, is not operating normally, i.e., that the drive voltage of the internal circuit (the output voltage Z of the filter circuit 903) is too low. Thus, the true/false judgment circuit 906 feeds the adder 907 with a signal S1 that increments the value of the signal NB by one to increase the drive voltage.
If the true/false judgment circuit 906 receives the delayed data through the delay circuit 905, the true/false judgment circuit 906 judges that the internal circuit, to which the supply voltage is being supplied, would operate normally even if a delay were given thereto, i.e., that the drive voltage of the internal circuit is too high. Thus, the true/false judgment circuit 906 feeds the adder 907 with a signal S2 that decrements the value of the signal NB by one to decrease the drive voltage.
If the true/false judgment circuit 906 receives the data directly from the critical path circuit 904 but does not receive the delayed data through the delay circuit 905, the true/false judgment circuit 906 judges that the internal circuit, to which the supply voltage is being supplied, is being supplied with the optimum drive voltage. Thus, the true/false judgment circuit 906 feeds neither the signal S1 nor the signal S2 to the adder 907.
When fed with the signal S1 from the true/false judgment circuit 906, the adder 907 feeds the duty ratio control circuit 901 with a value obtained by adding 1 to the current value of the signal NB. By contrast, when fed with the signal S2 from the true/false judgment circuit 906, the adder 907 feeds the duty ratio control circuit 901 with a value obtained by adding −1 to the current value of the signal NB.
In this way, in the voltage conversion circuit configured as described above, the operation rate of the internal circuit that is the target to which the supply voltage is supplied is detected by the critical path circuit 904, delay circuit 905, and true/false judgment circuit 906, and the duty ratio of the voltage signal Y is controlled in such a way that, if the detected operation rate is too high, the drive voltage of the internal circuit (the output voltage Z) is decreased and that, if the detected operation rate is too low, the drive voltage of the internal circuit (the output voltage Z) is increased.
It is true that the voltage conversion circuit configured as described above can monitor the operation status of the internal circuit constituting an integrated circuit and feed the internal circuit with the minimum drive voltage that it requires for normal operation. This contributes to reducing the power consumption of the integrated circuit. Moreover, the voltage conversion circuit permits its output voltage Z to be varied in a wide range, and is therefore useful as a voltage step-down circuit for common integrated circuits.
Incidentally, for further reduction of the power consumption of the internal circuit, it is very effective to reduce the supply voltage to the devices themselves that constitute the internal circuit. For example, the power consumption of an internal circuit employing devices operating from a supply voltage of 0.5 V is 1/36 of the power consumption of an internal circuit employing devices operating from a supply voltage of 3 V. Thus, it is possible to achieve still lower power consumption by reducing the supply voltage to the internal circuit and by reducing the load current.
As the power consumption of the internal circuit is reduced, on a relative basis, the proportion of the power consumption of the voltage conversion circuit in the power consumption of the integrated circuit as a whole increases. Therefore, for further reduction of the power consumption of the integrated circuit as a whole, it is necessary to reduce the power consumption of the voltage conversion circuit itself.
One way to reduce the power consumption of the voltage conversion circuit configured as described above is to limit the variable range of the output voltage Z and thereby simplify the control and reduce the scale of the duty ratio control circuit 901, adder 907, and other circuits.
For example, in a case where power is supplied from a voltage conversion circuit that is supplied with an external supply voltage of about 3 V to an internal circuit that operates from 0.5 V, it is not necessary to feed the internal circuit with a high voltage close to the input voltage. Moreover, the devices constituting the internal circuit have their optimum operation voltage, and therefore, even with allowances made for variations originating from the fabrication process and variations in operating conditions, it is possible to limit the variable range of the output voltage Z to closer around their optimum operation voltage. By limiting the variable range of the output voltage Z in this way, it is possible to reduce the circuit scale of the voltage conversion circuit and thereby reduce its power consumption.
However, in a voltage conversion circuit adopting the pulse width varying method, in which the value of the signal NB fed from the adder 907 to the comparator circuit is varied so as to vary the turn-on time T1 (the pulse width) and thereby control the duty ratio of the voltage signal Y output from the buffer circuit 902, even when the variable range of the output voltage Z is limited, it is still necessary to provide a counter that operates at a high rate.
For example, in the conventional voltage conversion circuit configured as described above, the counter circuit operates at 2n times (when n=6,64 times) the frequency of the voltage signal Y. Using a counter circuit that operates at such a high rate leads to an increase in the power consumption of the voltage conversion circuit itself, but keeping the counter circuit operating at a high rate is essential to vary the output voltage Z with high accuracy.
Thus, with the conventional voltage conversion circuit adopting the pulse width varying method, even if the variable range of the output voltage Z that is fed to an internal circuit operable from a low voltage is limited, the counter circuit needs to be kept operating at a high rate, and this makes it impossible to satisfactorily reduce the power consumption of the voltage conversion circuit itself.